Clock signals are well known in the art for controlling and synchronizing the operation of electronic circuits and systems. In a typical case there will be a master or system highest frequency clock signal from which all other lower frequency clock signals are derived. These various clock signals are distributed throughout the electronic system and are provided to various types of circuits, such as microprocessors, input/output circuits, analog-to-digital and digital-to-analog converts, dynamic memory controllers and the like.
A modern wireless communications terminal, such as a cellular telephone, is a complex data processing system that requires accurate and reliable clock signals. As an example, in the evolving third generation (3G) terminals the system the system clock is increased to 38.4 MHz, and is utilized by the baseband processing circuitry for sampling the received and transmitted signals. The increase in the frequency of the system clock is due at least in part to the higher dynamic range requirement of the RF interface analog-to-digital converter(s) (ADC) and digital-to-analog converter(s) (DAC). These circuits are used to convert the received In-phase and Quadrature (RX I/Q) signals and the transmitted I/Q (TX I/Q) signals from analog-to-digital and from digital-to-analog, respectively. The system clock may be generated from a crystal oscillator, in a well-known fashion.
The RF interface ADC and DAC require a high quality clock signal, i.e., one having low jitter and a repeatable and stable duty cycle. As may be appreciated, as the system clock frequency is increased it becomes more difficult to provide the desired high quality system clock signal.
In an exemplary application the system clock, when generated by a crystal oscillator circuit, is intended to be a pure sine wave at the desired frequency. However, in practice the system clock signal will also contain undesired harmonic frequencies. These harmonic frequencies and other error sources tend to cause the generation of a non-ideal duty cycle in the clock signal fed to the baseband circuitry, including the ADC and the DAC. In fact, the actual duty cycle variation may be ±10% or even more.
It can be realized that as the system clock frequency is increased the ADC and DAC conversion and cycle times are decreased proportionately, making the clock duty cycle requirement more critical. Typically one half of the clock signal is used for sampling the input signal to be converted which, at a clock frequency of 38.4 MHz, translates to about 13 nanoseconds. If one then factors in the possible worst case duty cycle variations, the actual converter sampling times can be reduced to less than 12 nanoseconds. As is well known in the art, as the converter sampling times are reduced the converter cost, complexity and power consumption typically increase, in order to maintain a desired level of performance. As a general rule, a doubling of the sampling frequency results in a four times increase in power consumption. In a portable, battery powered device, such as a wireless communication terminal, any increase in power consumption is detrimental, as it can translate to reduced talk and standby times.
One technique for correcting the clock signal duty cycle variation is through the use of a phase locked loop (PLL) circuit. However, and depending on the implementation, the use of the PLL can increase the clock signal jitter (indeterminancy in the occurrence of the clock signal edges), which is unacceptable from the point of view of the baseband converters. An increase in clock signal jitter typically results in an increase in complexity and cost in order to compensate the converter circuits for the jitter.